(1) Field of the Invention
The invention relates to a fault masking method for non-volatile memories, and especially relates to a fault masking method for non-volatile memories using the address scrambling.
(2) Description of the Prior Art
Non-volatile memory is one of the most important kinds of semiconductor memory in the world. It is widely used in the mobile computing products which require high-performance and low-power features. The main characteristic is that the stored data may not disappear after the power is turned off. Therefore, its production value is quite high after integrated with microcontrollers and digital processors. The non-volatile memory includes magneto-resistive random access memory (MRAM), read-only memory (ROM), flash memory, and phase change memory (PCM). Due to the rapid growing of information flows, the data transfer rate also keeps rising significantly. This increases the demands of high-capacity memories. However, during the manufacturing process of non-volatile memories, sophisticated defects will affect the yield of the manufactured products. In order to improve the production yield of memory products and reduce the costs of production, the world-class foundries have developed test and repair solutions, which use the redundant memory to replace faulty memory cells while the memory products fail the test phase.
The conventional memory array with the repair function incorporated usually records the locations of faulty cells during production test and then blows the fuses by the laser-cut equipment. Therefore, an entire memory column (or row) of the redundant memory can be used to replace an entire column (or row) of the main memory which contains faulty bits. FIG. 1A shows an example for the usage of spare columns. During the test phase for a memory array, faulty memory cells usually can be detected. The behaviors of the defects can be categorized into the stuck-at 1 or the stuck-at 0 faults. That is, the read out data is a constant 1 or 0, respectively. If column 1 contains the faulty cell 101, it will be regarded as a faulty column and mapped to the spare column A. We should find a way to record this mapping such that the faulty column will not be used. Due to the re-mapping operation, the processor will not access column 1 but the spare column A instead. The replaced cell 102 is used to replace the faulty cell 101. In addition, the other memory cells of the spare column A should also be used to replace other fault-free cells of column 1.
FIG. 1B is a memory system 200 used to illustrate the operations of the spare columns shown in FIG. 1A. After the test phase, it blows a fuse to indicate the position of the faulty column. Every memory column of the memory array 221 contains a fuse. When the memory system 200 starts operations, it will read out the contents of the fuses 220 and store into the control register 222. The contents of the control register 222 then indicate the locations of faulty columns and the allocated spare columns. When the host sends a memory access instruction, it will compare the accessed address with the stored faulty column addresses stored in the control register 222. If the comparison result indicates that there is a faulty column, it will access from the spare column, rather than attempt to access from the faulty column. Therefore, the control register 222 may provide a spare column address to the address decoder 224, and may not access from the faulty column. Multiple faulty columns can also be repaired by this way. Generally, we can provide a plurality of spare columns 226 to replace multiple faulty columns. Although, the conventional memory with the repair mechanism 200 can significantly improve the yield of the manufacturing process, the hardware overhead of the incorporated spare memory is still relatively high, resulting in a larger volume and the application is limited. Moreover, the replacement mechanism can only achieve a relatively lower yield in the manufacturing process as we consider more sophisticated fault mechanisms.